1. Field of Invention
The present invention relates to systems and methods for decoding baseband-encoded digital data.
2. Background
In many applications, it is desirable to reliably transmit digital data encoded in such a manner that the clock signal and data signal are contained within one signal. That permits remote transmission in situations where the receiver is not synchronized to the transmitter, and where transmitting an additional signal containing just the clock signal is not feasible due to skew or channel constraints. There are, of course, several possible encoding schemes for combining the clock and data signal. The two most frequently used baseband methods are biphase encoding and Manchester encoding. Those two encoding schemes and others can be derived from one another, such that most of the encoding and decoding methods that are applicable to any of those baseband schemes may be applied with some small transformation to the other baseband encoding schemes.
Those, encoding schemes involve frequency modulating a pulse train in accordance with a data signal. In biphase coding, the pulse train carrier is generated such that each transition represents the start of a new clock cycle. The carrier is further modulated by adding an extra transition in the middle of the clock cycle if the corresponding data signal is a one. The lack of a mid-cycle or mid-bit transition represents a data signal of zero. In biphase code, the directions of the transitions are ignored in the decoding process.
Circuitry for decoding combined data and clock signals for those schemes have been designed. However, the complexity of the circuits necessary for decoding encoded signals is dependent upon the degree of noise immunity desired. Whenever a signal is transmitted, it is affected by energy present in the environment, referred to as noise, which tends to distort the signal. That distortion typically manifests itself by skewing the edges of the signal. In order to recover the original data that was transmitted, it is necessary to examine the received signal to determine which transmitted value could be distorted with the smallest amount of noise to result in the signal received. That is, a decision must be made as to which transmitted value is most probable. The effectiveness with which that decision is made determines the noise immunity of a particular circuit.
There are two primary methods for accomplishing the decoding: analog and digital. The analog methods use analog circuitry such as an analog phase-locked loop to recover the clock information present in the transmitted signal. That recovered clock information is then used to determine the data values in the signal. The digital methods generally use an external decoder clock operating at a frequency that is approximately equal to a multiple of the transmitted clock frequency. That clock is used to sample the transmitted signal at various points. Those samples are then used to determine the clock value and data value embedded in the combined signal by detecting transitions within the signal. Since the approximate frequency of the transmitted clock signal is known, a transition followed by another transition one transmitted clock period later can be decoded as a zero data signal and one transmitted clock cycle. The second transition is then regarded as the start of another bit cycle. If the next transition occurs at the end of the bit cycle, another zero is decoded. On the other hand, if the next transition occurs in the middle of the bit cycle, a one is decoded with the following transition marking the start of a new bit cycle. Because of both sampling error and skewing of the signal edges, however, transitions may not occur or be detected at precisely the times indicated above. In such cases, the transition is decoded as that transmitted value which is the most probable to have been transmitted. For example, a transition occurring before 3/4-bit time is read as a one, while a transition occurring after 3/4-time is read as a zero and the start of another bit cycle. It is ambiguous, however, whether a transition occurring within a sample containing the 3/4-bit time should be decoded as a one or a zero.
For digital decoding, a clock operating at some multiple of the transmitted clock frequency is used to take some number of samples per bit cycle of the input signal. As the number of samples per bit is increased, the amount of data available for making the decoding decision is increased such that it is possible to gain greater noise immunity. The cost for doing so, however, is that a clock operating at a higher frequency must be built, and the decoding circuit must be able to operate at a correspondingly faster speed. Operation at higher speeds typically requires more expensive and carefully designed circuitry. In some cases, commercially available components cannot be found to operate at such speeds.
Systems and methods for decoding baseband-encoded digital signals have been developed to provide for more reliable decoding in the presence of noise. One such system is disclosed in U.S. patent application Ser. No. 07/244,642, filed on Sept. 12, 1988, and assigned to Schlumberger Well Services, which is hereby incorporated by reference into the present application. In the system described in that application, a "look ahead" scheme is used to defer decoding decisions for transitions occurring within samples containing the 3/4-bit time until 1/2-bit time later. That system, however, measures the bit time used to make decoding decisions from detected bit-boundary transitions. Skewing of those bit-boundary transitions can, therefore, result in performance degradation since the bit times will then not be measured correctly.